1. Field of Invention
The present invention relates to a chip package structure. More particularly, the present invention relates to a hybrid integrated circuit (IC) carrier for a chip package structure.
2. Description of Related Art
With great advance in the electronic technology in recent years, many high-tech electronic products are out in the market. Many electronic products are multi-functional, compact and increasingly personalized to fit a particular need. At present, integrated circuit (IC) carrier is a major component in packaging a semiconductor chip. The IC carrier is a substrate comprising a plurality of patterned conductive layers and a plurality of dielectric layer alternately stacked and laminated over each other. The dielectric layer is positioned between two neighboring patterned conductive layers. The patterned conductive layers are electrically connected through plating through hole in the dielectric layer or conductive vias. Because the IC carrier has many advantages including compact wiring, tight assembly and superior electrical properties, it has become a mainstream substrate for packaging chips.
At present, the two principle methods of packaging a chip includes wire bonding and flip chip bonding. FIG. 1 is a schematic cross-sectional diagram showing the structure of a conventional flip chip package. As shown in FIG. 1, the chip package 100 comprises an integrated circuit carrier 110 and a chip 120. The chip 120 is set up on the first surface 112 of the IC carrier 110. Through a plurality of bumps 126, the chip 120 is electrically connected to the contact pads 116a on the IC carrier 110. In addition, the IC carrier 110 has a plurality of contacts 118 on the second surface 114 of the IC carrier 110. The contacts 118 are solder balls, contact pins or metallic bumps, for example. Furthermore, the contacts 118 are connected electrically to corresponding bumps 126 via the patterned circuit layer 130 in the IC carrier 110. Hence, these contacts 118 serve also as point of contact between the chip 120 and the contacts on a printed circuit board (not shown). Additionally, the IC carrier 110 can be classified as an organic substrate or a ceramic substrate according to the dielectric material used. The production method and electrical properties for these two types of substrate differ considerably, and thus each type of substrate has a particular area of use. The organic substrate is fabricated using material including glass epoxy resin (FR-4, FR-5), bismaleimide-triazine (BT) or epoxy resin. The organic substrate can be a multi-layered substrate fabricated using a lamination and/or a build-up method. On the whole, the fabrication cost of the organic substrate and the dielectric constant of an organic substrate are lower than a ceramic substrate. Consequently, the organic dielectric substrate is used to be the only option for fabricating chip packages chips and manufacturing printed circuit boards.
FIG. 2 is a schematic cross-sectional view of a portion of a conventional chip package substrate. An organic dielectric substrate 210 with six (2-2-2) conductive layers is used as an example. A dielectric layer 202 is formed between every pair of neighboring patterned conductive layers 214. The dielectric layer 202 comprises a dielectric core layer 202(c). Organic dielectric layers 202(b) and 202(a) are sequentially formed on the upper surface of the dielectric core layer 202(c) using a built-up method, for example. Similarly, organic dielectric layers 202(d) and 202(e) are sequentially formed on the lower surface of the dielectric core layer 202(c) using a built-up method. A plurality of plated through holes (PTH) 216 pass through the dielectric core layer 202(c) such that the two terminals of the plated through hole 216 connect electrically with two patterned conductive layers 214(c) and 214(d) respectively. Additionally, a plurality of vias 218 are buried in the organic dielectric layers 202(a), 202(b), 202(d), 202(e) outside the dielectric core layer 202(c) for connecting two neighboring patterned conductive layers 214(a), 214(b), 214(c) or 214(d), 214(e), 214(f). Moreover, the outermost patterned conductive layers 214(a) and 214(f) each has a plurality of bonding pads 220a and 220b. The bonding pads 220a are used for connecting with the bumps (not shown) on the chip. A plurality of contact 222 is also attached to the surface of the bonding pads 220b for connecting to corresponding contacts on a printed circuit board (not shown).
FIG. 3 is a schematic cross-sectional view of a portion of another conventional chip package substrate. An organic dielectric substrate 230 with six (1-4-1) conductive layers is used as an example. A dielectric layer 232 is set up between each pair of neighboring patterned conductive layers 234. The dielectric layer 232 includes a dielectric core layer 232(c). Organic dielectric layers 232(b) and 232(d) are formed on the upper and the lower surface of the dielectric core layer 232(c) using a lamination method, for example. Thereafter, organic dielectric layers 232(a) and 232(e) are formed on the outermost layers using a built-up method, for example. In addition, a plurality of plated through holes (PTH) 236 pass through the dielectric core layer 232(c) and the two organic dielectric layers 232(b) and 232(d). Furthermore, the plated through holes 236 also connect any two of the stacked patterned conductive layers 234(b), 234(c), 234(d), 234(e) electrically. Moreover, a plurality of vias 238 is buried within the outermost organic dielectric layers 232(a) and 232(e). The vias 238 are respectively connected to two neighboring patterned conductive layers 232(a) and 232(b) or 232(e) and 232(f). Moreover, each the outermost patterned conductive layers 234(a) and 234(f) has a plurality of bonding pads 240a and 240b. The bonding pads 240a are used for connecting with the bumps (not shown) on the chip. A plurality of contacts 242 are also attached to the surface of the bonding pads 240b respectively for connecting to corresponding contacts on a printed circuit board (not shown).
As shown in FIG. 1, the conventional IC carrier 110 has a dielectric core layer 132 having a thickness of about 800 μm. The dielectric core layer 132 is fabricated using fiber material and organic resins to increase the hardness of the IC carrier 110. However, a mechanically drilled plated through hole 136 is limited by the material constituting the dielectric core layer 132 to a smallest diameter of about 250 μm. Consequently, there is a limitation on the circuit density of the patterned circuit layers 130, 134 on two sides of the dielectric core layer 132. Moreover, pitches of two neighboring plated through holes 136 must be grater than 550 μm. Hence, the wiring length in the patterned conductive layers 130, 134 connecting the bonding pads 116a, 116b must be increased leading to a longer signal transmission path inside the package.
Therefore, a chip package substrate capable of cramming more wires per unit area and having more wires with a shorter length is an important precondition for fabricating a chip package with high-density circuits and high pin count.